||The rapid development of high-speed digital circuits leads to high complexity of layout design and the accompanying signal integrity problems, and presents a very serious challenge in packaging technology. The state-of-the-art FOWLP (Fan-Out Wafer Level Package) packaging technology assembles 2 to 3 bare chips inside a package using extremely fine lines (2~4 um) linking the chips, the package is then connected to an organic substrate with FC bump or conventional 25 um line to form a hybrid package. However, when high-speed signals travel on the extremely fine line, the impedance characteristics becomes very difficult to control compared to conventional packaging technology. Further, the crosstalk resulting from the extremely close proximity among signal lines and the conductor loss of copper wires due to skin effect are no longer negligible. Moreover, the dielectric loss of the organic substrate and the roughness of the copper line surface all make the design of hybrid packaging even more challenging.|
This thesis focuses on the characterization of next-generation 100Gbps differential signal line structures. Effects of factors such as characteristic impedance, line widths, line separations, and roughness of the organic substrate and copper wires on the performance of crosstalk, insertion loss, return loss, eye diagram and jitter are thoroughly investigated to present suggestions on guidelines of optimal designs.