Title page for etd-0614101-164407


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URN etd-0614101-164407
Author Lan-Chi Lee
Author's Email Address m8831676@student.nsysu.edu.tw
Statistics This thesis had been viewed 5353 times. Download 1818 times.
Department Electrical Engineering
Year 2000
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Improving Workload Balance and Code Optimization on Processor-In-Memory Systems
Date of Defense 2001-05-29
Page Count 52
Keyword
  • statement
  • PIM
  • iteration
  • Abstract PIM (Processor-In-Memory) architectures have been proposed in recent years. One major objective of PIM is to reduce the performance gap between the CPU and memory. To exploit the potential benefits of PIM, we designed a statement base parallelizing system –SAGE in [1, 2]. In order to make all processors take the best-fit workload in PIM, iteration base analysis is another research issue in this paper. We extend this system to achieve better performance by devising several comprehensive optimizing techniques, which include IMOP (Intelligent Memory Operation) recognition, tiling for PIM, and a precise mechanism to get workload balance execution schedule. The experimental results are also presented and discussed.
    Advisory Committee
  • Shian-Shyong Tseng - chair
  • Chih-Ping Chu - co-chair
  • Nai-Wei Lin - co-chair
  • Yeh-Ching Chung - co-chair
  • Tsung-Chuan Huang - advisor
  • Files
  • etd-0614101-164407.pdf
  • indicate access worldwide
    Date of Submission 2001-06-14

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