Title page for etd-0613101-192127


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URN etd-0613101-192127
Author Hwa-Jyh Jean
Author's Email Address No Public.
Statistics This thesis had been viewed 5351 times. Download 3503 times.
Department Electrical Engineering
Year 2000
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Designing New Scheduling Mechanisms for Processor-in-Memory Systems
Date of Defense 2001-05-29
Page Count 63
Keyword
  • Scheduling
  • PIM
  • SAGE
  • Abstract Abstract
     Processor-in-memory (PIM) architectures have been proposed in the recent years. One major objective of PIM is to reduce the performance gap between the CPU and memory. To exploit the potential benefits of PIM, we designed a statement-base parallelizing system – SAGE(Statement-Analysis-Grouping-Evaluation) in [1][2][3]. From our pervious research, we find that the execution schedule is a critical factor to the performance of PIM systems. In this paper, we provide new scheduling mechanism for one-host and one-memory processors (1H-1M) and one-host and n-memory processors (1H-nM), respectively, to fully utilize all of the memory processors in PIM architectures. The experimental results of these two mechanisms are also discussed.
    Advisory Committee
  • Shian-Shyong Tseng - chair
  • Chih-Ping Chu - co-chair
  • Nai-Wei Lin - co-chair
  • Yeh-Ching Chung - co-chair
  • Tsung-Chuan Huang - advisor
  • Files
  • etd-0613101-192127.pdf
  • indicate access worldwide
    Date of Submission 2001-06-13

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