||In this thesis, a 10-bit resolution analog-to-digital converter with 100MHz sampling frequency is proposed. In terms of design, in order to improve the conversion speed, the 2b/cycle conversion is adapted in the conversion of the upper bits. Since three comparators are required to perform the 2b/cycle conversion, it may cause the increase of the error probability. Therefore, the proposed architecture adapts the non-binary correction technique in the upper bits to tolerate fault error and hence correct the error. In the lower bit conversion, a 1b/cycle conversion is implmented to increase the accuracy. Moreover, the architecture also adopted the alternate technique in lower bit conversion to improve the conversion efficiency. This technique not only uses the comparators more efficiently, but also relaxing the issue of the longer comparison time in the lower bit conversions. At last, a redundant bit is added in the lower bits to increase the fault tolerance capability of the lower bits.|
This thesis implements a 10-bit analog-to-digital converter with 100MHz sampling frequency by using the TSMC 90nm process technology. For the static analysis, the DNL and INL are +1.248 / -0.750 LSB and +1.679 / -1.677 LSB, respectively. For the dynamic analysis, the SFDR and SNDR at the Nyquist rate are 62.76 dB and 56.099 dB. The ENOB is 9.026 bit, the power consumption is 2.397 mW and FoM is 45.98 fJ / conv.-step.