||This thesis consists of two topics, including a single-ended disturb-free 5T load-less 4Kb SRAM, and the leakage current sensor and compensation circuit mainly designed for memories, e.g., the mentioned single-ended disturb-free 5T load-less SRAM.|
The first topic presents a single-ended disturb-free 5T load-less 4Kb SRAM. The single-ended load-less SRAM cell consist of 5 transistors, where a write assistant loop and an isolated wordline-controlled transistor (WLC) are integrated therewith. The proposed cell is proved to attain the smallest area and disturb-free during the memory access. A shared bitline inverter is included to boost the read access speed at the minimal expense of area cost. Furthermore, a build-in self-test (BIST) circuit is included in the memory for testable R/W access. Based on the on-silicon measurements, the proposed 5T 4Kb SRAM shows superior performance in terms of power per access after normalization of the technology parameters.
The second topic discloses a leakage current sensor and compensation circuit, consisting of a SRAM cell model, a reference voltage circuit, a comparator and the compensation circuit. The circuit is implemented in the mentioned single-ended disturb-free 5T load-less 1Kb SRAM. When the leakage current seriously endangers the state of the data bit, the sensor will notify a warning message to the compensation circuit and wake it up to refresh the corresponding bit. This circuit is proven to reduce 27.86% of the power consumption and boost 36.68 % of the speed during read access based on all-PVT-corner post-layout simulations results.