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URN etd-0609115-192651
Author Wen-Je Lu
Author's Email Address No Public.
Statistics This thesis had been viewed 5351 times. Download 0 times.
Department Electrical Engineering
Year 2014
Semester 2
Degree Ph.D.
Type of Document
Language English
Title Mixed-Voltage Output Buffer with Process, Voltage, and Temperature Detectors for Slew Rate Compensation
Date of Defense 2015-06-29
Page Count 95
Keyword
  • corner
  • skew inverters
  • slew rate
  • output buffer
  • high operating speed
  • complementary metal-oxide-semiconductor
  • Abstract Many digital devices such as universal serial bus, bluetooth, and digital audio player have been widely used in human daily life. Nanoscale complementary metal-oxide-semiconductor (CMOS) technology to realize these devices undoubtedly provides many advantages, such as high operating speed, low power consumption, and small area for system-on-chip integration. However, problems associated with advanced nanoscale CMOS technology such as process, voltage, and temperature variations will become devastating in the technology evolution. Thus, this thesis proposes the process, voltage, and temperature compensation technologies, which can be applied to nanoscale CMOS, particularly, 2xVDD output buffers.
        A 2xVDD output buffer with a PVT detector for slew rate compensation is firstly introduced. The proposed PVT sensor is used to detect PVT corners of the buffer.According to the detected PVT corners, the PVT decision circuit turns on different current paths within the 2xVDD output buffer to compensate for the slew rate. Furthermore, the proposed design implemented by 1xVDD devices attains 2xVDD output range.
        Particularly, process corner sensors consisting of skew inverters for the 2xVDD output buffer are also investigated. The proposed process sensors take advantage of different transfer characteristics of skew inverters to separate the p-type and n-type MOS’s F and S corners. According to the detected PVT corners, the PVT decision circuit correspondingly turns on different current paths within the 2xVDD output buffer to compensate for the slew rate.
        Finally, the proposed 2xVDD output buffers are implemented using CMOS processes to justify their performance. Notably, the slew rate is significantly improved when the 2xVDD output buffer is supported by a PVT sensor for slew rate compensation and skew inverters for process corner detection. The maximum slew rate improvements are 26% and 8%, respectively, justified by physical measurements.
    Advisory Committee
  • Chin-Long Wey - chair
  • Soon-Jyh Chang - co-chair
  • Tzyy-Sheng Horng - co-chair
  • Tong-Yu Hsieh - co-chair
  • Ko-Chi Kuo - co-chair
  • Chua-Chin Wang - advisor
  • Files
  • etd-0609115-192651.pdf
  • Indicate in-campus at 99 year and off-campus access at 99 year.
    Date of Submission 2015-07-09

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