Title page for etd-0608113-213119


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URN etd-0608113-213119
Author Deng-Shian Wang
Author's Email Address No Public.
Statistics This thesis had been viewed 5352 times. Download 79 times.
Department Electrical Engineering
Year 2012
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS
Date of Defense 2013-06-27
Page Count 73
Keyword
  • BMS
  • high-voltage multiplexer
  • charge redistribution architecture
  • successive-approximation register ADC
  • high-voltage switch
  • Abstract This thesis includes two designs: A high-voltage (HV) multiplexer and a successive-approximation register ADC for Battery Management Systems (BMS). The proposed designs are implemented by using TSMC 0.25 μm 60V HV CMOS process, and verified by physical measurements.
      Though the first topic presents a high-voltage multiplexer which is fabricated using an advanced high-voltage (HV) semiconductor process, the HV process usually is constrained by the voltage drop limitation between gate and source of HV CMOS transistors. To overcome such a limitation, a high-voltage switch is proposed in this work, including two gate voltage drivers and a buck converter driving the HV devices without causing any over-voltage hazard. Based on the system requirements, the output range of the HV multiplexer should be covered by the input range of the following ADC. The multiplexer employs a divider & subtracter and a multiplier to carry out such a function. The entire design is designed for the voltage detection circuit in the Battery Management Systems, where the voltage detection error is verified to be less than 10 mV by simulations.
      The second topic discloses a successive-approximation register ADC for the voltage detection as well in the Battery Management Systems. Due to the gentle variation of the battery voltage characteristic, an ADC with 20 KHz sampling rate and 12–bit resolution is proposed and used in the detection circuit. To reduce the capacitor size in the ADC, a single capacitor array based on the charge redistribution architecture is used in the proposed ADC. By the simulation results, the integral nonlinearity (INL) and the differential nonlinearity (DNL) of the proposed ADC are both less than two LSBs such that the error is less than 1 mV.
    Advisory Committee
  • Soon-Jyh Chang - chair
  • Tzyy-Sheng Horng - co-chair
  • Ko-Chi Kuo - co-chair
  • Chua-Chin Wang - advisor
  • Files
  • etd-0608113-213119.pdf
  • Indicate in-campus at 5 year and off-campus access at 5 year.
    Date of Submission 2013-07-10

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