Title page for etd-0514118-221744


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URN etd-0514118-221744
Author Chao-Yi Hsu
Author's Email Address No Public.
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Department Computer Science and Engineering
Year 2017
Semester 2
Degree Master
Type of Document
Language English
Title Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform
Date of Defense 2018-01-19
Page Count 67
Keyword
  • Multiprocessor
  • SystemC
  • Performance Analysis
  • SH/HW Co-verification
  • QEMU
  • Abstract With the rapid development of multi-processor embedded system, design and verification of hardware/software become more complex. The developers of software and hardware integration raise the abstraction level of validation and integration phase from Register Transfer Leve (RTL) to Electronic System Level (ESL). The process of validation and integration can be accelerated significantly in ESL. QEMU-SystemC emulation platform is widely used in the ESL, and it can emulate many different multi-processor architectures for performance analysis or behavior verification. The latest version of QEMU can emulate the target processors which already mapping to the thread of the host machine for executing the emulation workload. Thus, each emulated CPU on target platform can be executing on the host machine in parallel. This thesis demonstrates a full system emulator, which can target the multi-processor architecture with QEMU and SystemC, make emulated virtual CPUs runs on different threads to take full advantage of host machine computing resources, increasing the performance of emulator, also include the timing engine which can estimate the performance of the target system.
    Advisory Committee
  • Chung-Ho Chen - chair
  • Fu-Ching Yang - co-chair
  • Shi-Wu Lo - co-chair
  • Tong-Yu Hsieh - co-chair
  • Ing-Jer Huang - advisor
  • Files
  • etd-0514118-221744.pdf
  • Indicate in-campus at 3 year and off-campus access at 3 year.
    Date of Submission 2018-06-15

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