Title page for etd-0413110-033402


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URN etd-0413110-033402
Author Fu-yen Jian
Author's Email Address No Public.
Statistics This thesis had been viewed 5366 times. Download 1971 times.
Department Electro-Optical Engineering
Year 2009
Semester 2
Degree Ph.D.
Type of Document
Language zh-TW.Big5 Chinese
Title Novel Nonvolatile Memory for System on Panel Applications
Date of Defense 2010-03-25
Page Count 125
Keyword
  • Nonvolatile memory
  • Active matrix flat-panel displays
  • System on panel (SOP)
  • Silicon-oxide-nitride-oxide-silicon
  • Polysilicon thin-film transistors
  • Abstract Recently, active matrix flat-panel displays are widely used in consumer electronic products. With increasing popularity of flat-panel displays, market competition becomes more intense and demands for high performance flat-panel displays are increasing. Low-temperature polysilicon (LTPS) with higher mobility, as well as drive current can integrate electric circuit, such as controllers and memory on glass substrate of display to achieve the purpose of system on panel (SOP). Thus, flat-panel displays can be more compact, while reducing reliability issues and lowering production costs.
    In this dissertation, we studied the nonvolatile memory for system on panel applications and reducing cost of memory by increasing the memory density or reducing the processing steps. Therefore, we proposed several modes of operation in nonvolatile memory.
    First, we use channel hot-electron (CHE) to inject electrons into the nitride layer that’s above source or drain sides of SONOS thin film transistor (TFT). Thus, we can increase the memory density by storing two-bit state in a memory cell. In this study, the two-bit memory effect is clearly observed for devices with a shorter gate length after CHE programming; however, the two-bit memory effect is absent in devices with a longer gate length. The gate-length-dependent two-bit memory effect is related to the location of injected electrons in the nitride layer. When electrons are injected into the nitride layer above the channel, they can create an additional energy barrier in the channel thus increasing the threshold voltage of the device to perform the programming operations. However, if electrons are injected into the depletion region at the P-N junction between the drain and the channel, the energy barrier induced by electrons is not significant when exchanging the source and drain electrodes to measure the memory status, and the program effect is not as significant. When the channel length is shorten, the built-in potential between the source and the channel can be decreased, the energy barrier caused by programmed electrons can affect electrons in the channel and increase the threshold voltage. Therefore, the two-bit memory effect can be seen in devices with the shorter gate length after CHE programming.
    Secondly, we stored charges in the body of the thin film transistor to make the conventional thin-film transistors become a non-volatile memory. This method does not need a floating gate or a tunneling oxide in the memory cell; therefore the memory cost can be reduced. In this study, we used trap-assisted band-to-band thermionic field emission enhanced by self-heating in TFT to produce electron-hole pairs. The hole will be separated by a vertical field under the gate and be injected into the body of TFT to complete the programming operation. The erasing operation is performed by applying a lateral electric field between the source/drain to remove holes in the body of TFT.
    Thirdly, we proposed an edge-FN tunneling method to allow SONOS TFT possess not only a pixel switch but also a two-bit nonvolatile memory function in a display panel, thus causing the memory density to increase. In this study, we used a channel FN tunneling to program the SONOS TFT. Because the electric field in the gate-to-drain overlap region is larger than that in the channel region, it will cause a smoother electron injection into the nitride layer inside of the gate-to-drain overlap region, which also increases the gate-induced drain leakage (GIDL) current. The edge-FN tunneling method is used to erase electrons in the gate-to-drain overlap region, by doing so, the GIDL current has decreased. The memory status at the source/drain side is determined by the corresponding GIDL current of the SONOS TFT.
    Fourthly, we stored electrons in the nitride layer at source, channel, and drain regions of SONOS TFT to make sure that TFT possess a three-bit memory effect in a unitary cell, which also allows the memory density to increase significantly. In this study, programming and erasing operations in the source/drain region are performed by channel hot-electron injection and edge-FN tunneling method, while that in the channel region are accomplished by channel FN tunneling. The memory status in the source/drain is determined by the corresponding GIDL current, while that in the channel region by threshold voltage of the device The memory density for the device operated by proposed method can be further increased.
    In addition, if we store a number of N different types of electrons in those three regions mentioned above, there are N3 status can be stored in a memory cell. The memory density can beyond conventional multi-level-cell (MLC) flash memory. Two-bit memory effect per cell in a MLC flash memory can be achieved by storing four quantitative electrons in the floating gate of the memory device. If we store four quantitative electrons in the nitride layer at source, channel, and drain regions of SONOS TFT, we can obtain 64 memory states or 6-bit memory effect in a memory cell. Thus, the proposed concept is promising to storage the messages in a memory cell beyond four-bit.
    Advisory Committee
  • Ching-Ting Lee - chair
  • Shoou-Jinn Chang - co-chair
  • Ming-Kwei Lee - co-chair
  • Ying-Chung Chen - co-chair
  • Ting-Chang Chang - advisor
  • Ann-Kuo Chu - advisor
  • Files
  • etd-0413110-033402.pdf
  • indicate in-campus access immediately and off_campus access in a year
    Date of Submission 2010-04-13

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