Title page for etd-0224114-122630


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URN etd-0224114-122630
Author Rou-Jia Chen
Author's Email Address No Public.
Statistics This thesis had been viewed 5359 times. Download 450 times.
Department Computer Science and Engineering
Year 2013
Semester 2
Degree Master
Type of Document
Language English
Title A Study of the Limits of Parallelism Available in SIMD Processors Through Register Packing
Date of Defense 2014-01-27
Page Count 92
Keyword
  • register allocation
  • loop unrolling
  • SIMD and vector processing
  • instruction scheduling
  • Abstract This thesis designed an instruction-level-parallelism processor for the embedded system with general purpose computations. The hardware of the embedded system is small-scalar then currently popular CPU or GPU. We exploit some techniques to enhance the instruction scheduling time of our SIMD processor.
      
    By applying branch-and-bound ways to modify algorithm that maintain optimality includes PRSR (pseudo random shift register), memorization, and register grouping.  And we also support heuristic ways that is a mental shortcut that allow us to solve exhaustive searching quickly and efficiently such as unrolling optimization, instruction distribution, and sign constraint. 
      
    Through register packing and loop unrolling, we applied our SIMD processor on Mibench and have a compatible performance with VLIW processor; moreover, our register packing allows for a vector-wide load from the SRAM. Such a load is a natural fit to a SIMD and achieves significant speedups, when our allocator is used.
    Advisory Committee
  • Chungnan Lee - chair
  • Chun-Hung Lin - co-chair
  • Tong-Yu Hsieh - co-chair
  • Steve W. Haga - advisor
  • Files
  • etd-0224114-122630.pdf
  • Indicate in-campus at 1 year and off-campus access at 2 year.
    Date of Submission 2014-03-26

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