||There are three parts in this thesis:|
In the first part (Chapter 2), we discuss the port excitation (Wave port vs Lumped port) suitable for sub-millimeter wave operations. We realized on printed circuit board a grounded coplanar waveguide (CPWG) and on gallium arsenic (GaAs) a microstrip line. We performed simulation on these structures using high frequency structure simulator (HFSS), and compared the results with measured ones. From the comparison, we found close match for CPWG insertion loss from 10 MHz to 67 GHz using the Wave port. However, for G-S-G lumped port, only matched up to 40 GHz. The wave port not only was more accurate, but also consumed less time in simulation. Consequently, we employed wave port as our simulation excitation for our sub-millimeter wave QFN design.
In the second part (Chapter 3), we focused on design of low cost QFN for sub-millimeter wave applications. We fabricated test structures, which include IC pads and transmission lines, wire bonds, QFN leads, and G-S-G structures on printed circuit board. In HFSS simulation, our specially designed ribbon bonds and QFN configuration show return loss less than -20dB and insertion loss less than -0.4 dB up to 60 GHz. Using the same design principles, we strived to improve the performance of a commercially available QFN, which normally operates at 3 to 6 GHz. The extraction method to obtain the high frequency characteristics was introduced first, and the characteristics of a commercially available QFN (with our wire bond configuration) were then obtained. The insertion loss was less than -20 dB and insertion loss less than -0.5 dB up to 20 GHz. In Chapter 5, we discuss the performance discrepancies between the simulated ribbon bond results and that for fabricated wire bonds.
In the third part (Chapter 4), we introduced a method to extract the characteristics of a single backside via and investigated the effects of die attachment on the performance of a single and multiple backside via(s). Using silver epoxy and Cu blank layer as die attach methods, we found it was important to provide a broad path (Cu blank layer), as opposed to a restrict path (like silver epoxy) to reduce the inductance of the backside vias.
The conclusion and future work are provided in Chapter 5.