Title page for etd-0202110-021248


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URN etd-0202110-021248
Author Tai-sheng Wang
Author's Email Address No Public.
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Department Mechanical and Electro-Mechanical Engineering
Year 2009
Semester 1
Degree Master
Type of Document
Language English
Title Lead Free Bump Assembly Material and Structure Study for 40 nm Wafer Technology
Date of Defense 2010-01-19
Page Count 69
Keyword
  • Underfill
  • Lead Free Bump
  • 40nm Wafer Technology
  • Reliability Test
  • Abstract Solder bump is used to connect organic substrate with chip to form Flip Chip package. Comparing to wire bond package, the path is reduced so the electrical performance is much better. Due to the environmental concern, eutectic bump is replaced by lead-free bump gradually. Meanwhile, since wafer technology is improved from 55 nm to 40 nm, the material for dielectric layers is also changed so the material for the package need to revised to meet the characteristic of wafer. Now the laser grooving is adopted before blade sawing to accommodate the brittleness of new 40nm wafer. Also, one extra polyimide is added in the wafer fabrication to reinforce the robustness of the circuit.
    The stress inside the lead-free bump can be reduced by optimizing the temperature of the reflow process and the speed of cooling. Different UBM structure is also reviewed to find out its affect on the strength of bump and low-K circuit so the failure mode of bump can be predicted. The selection of underfill need to be well considered so, the warpage of package can be reduced, the maximum protection of bump and low-K circuit can be achieved, and the process is easier to control. (The four underfills are reviewed) The reliability test is utilized to decide the best bump composition, the structure of UBM, the selection of underfills and the process parameter.
    By adding the laser grooving in the wafer sawing process, the chance of crack on die low-K layer is reduced during the reliability test. As for the UBM structure, the POU is better than RPI to reduce the crack of die low-K layer. The result is verified on the package with no underfill by Temperature cycle. Last, the matching of SnCu0.7 bump with SAC305 C4 pad has the best result.
    During the research, the variance of CTE for the core of substrate contributes less warpage of package, comparing to the difference of Tg for underfills. The adhesion of underfills varies and the underfill UA9 has the best result. The flip chip package with underfill UA9 can passes TCB1000. 
    The optimization of UBM structure for lead-free bump is researched and discussed. Composition of the lead-free bump, process parameter, and cost, those factors are also studied.
    Advisory Committee
  • Tseng, Yih-Tun - chair
  • Lin, Wei-Huang - co-chair
  • Young,Tai-Fa - advisor
  • Files
  • etd-0202110-021248.pdf
  • indicate in-campus access in a year and off_campus not accessible
    Date of Submission 2010-02-02

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