Title page for etd-0125111-154905


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URN etd-0125111-154905
Author Shin-Yang Lin
Author's Email Address No Public.
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Department Electrical Engineering
Year 2010
Semester 1
Degree Master
Type of Document
Language English
Title A CMOS LNA for 3.1-10.6GHz Ultra-Wideband
Date of Defense 2011-01-21
Page Count 63
Keyword
  • low noise amplifier
  • input matching
  • Series-peaking
  • Resistive-feedback
  • Ultra-wideband
  • CMOS
  • Abstract The objective of this thesis is aimed at the design of low noise amplifier (LNA) for
    an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process.
    A two amplified stage topology is proposed in the low noise amplifier. The first stage
    introduces inductively source degeneration, it can achieve wideband
    input impedance matching. The second stage introduces traditional CS configuration, it can
    improve the forward gain (S21). The second stage also used L-C section for output match.
    In order to improve the gain at high frequency, we introduces the series peaking between the
    first stage and second stage. We use the resistive-feedback between second stage and output, it can achieve wideband output impedance matching. The total power dissipation of the low noise amplifier is about 16.5mW at power supply 1.5 volt and the chip size is 920*940mm2. The simulated result shows that S11 is under -9dB, S22 is under -10dB, the forward gain S21 is 11.63dB~12.56dB at 3.1-10.6GHz, the reverse isolation S12 is under -32dB, and the noise figure is3.3dB~3.96dB.
    Advisory Committee
  • Tzyy-Sheng Horng - chair
  • Ko -Chi Kuo - co-chair
  • Chia-Hsiung Kao - advisor
  • Files
  • etd-0125111-154905.pdf
  • indicate in-campus access immediately and off_campus access in a year
    Date of Submission 2011-01-25

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