Title page for etd-0114114-151336


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URN etd-0114114-151336
Author Cheng-tao Wu
Author's Email Address No Public.
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Department Electrical Engineering
Year 2013
Semester 1
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Software Implementation of a Configurable Design of Control Units of Pipeline Processors
Date of Defense 2013-09-11
Page Count 72
Keyword
  • Verilog
  • computer aided design
  • architecture description language
  • controller
  • pipeline processor
  • Abstract CPU(Central Processing Unit) is one of the important parts in an electric computer. Controller definitely plays an important role in the CPU. Different processor architectures require different design composition of their controllers. Processor designers usually spend lots of design exploration effort in controller designs. In this research, we carried out automated design of controller design. We provide a description method of controller designs. Designers can thus easily express their high-level design decisions of the controller. The controller design of a processor can then be generated via automated design generation. In this research, we developed automated generation software of instruction decoder and control signal generator. We carried out design experiments of controller designs of RISC pipeline processors to verify correct new of the automated design software.
    Advisory Committee
  • Shiann-Rong Kuang - chair
  • Chen, Chih-Chien T. - co-chair
  • Tsung Lee - advisor
  • Files
  • etd-0114114-151336.pdf
  • Indicate in-campus at 1 year and off-campus access at 99 year.
    Date of Submission 2014-02-14

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