Title page for etd-0112104-170701


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URN etd-0112104-170701
Author Jian-Han Huang
Author's Email Address No Public.
Statistics This thesis had been viewed 5566 times. Download 6913 times.
Department Electrical Engineering
Year 2003
Semester 1
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title Fabrication and Simulation of the Cross-Gate SOI MOSFET
Date of Defense 2003-12-19
Page Count 65
Keyword
  • the Cross-Gate SOI MOSFET
  • 71nm
  • double sources and double drains
  • four channels SOI MOSFET
  • three surfaces of gate structure
  • Abstract In this thesis, the Cross-Gate SOI MOSFET that has double sources and double drains was successfully fabricated. The new SOI device structure has five unique features. First, it uses mesa isolation instead of using conventional LOCOS and trench isolation to avoid the bird’s beak effect in LOCOS isolation and the complexity of digging trench in trench isolation; second, it has three surfaces of gate structures which can increase the effective channel width of the device to enhance the current drivability of the device without reducing the packing density of the circuit; third, it has four channels which can increase the current drivability of the device; fourth, it has narrowed source and drain that can reduce the leakage current; fifth, it has double sources and double drains that can design double or half current in the electric circuit by one device.
    According to the simulation results of the TSUPREM-4 and TMA TCAD, the saturation drain current of the multi-gate SOI devices are almost double larger than that of the conventional SOI device as VGS - Vth = 0.7 V. And the threshold voltage、 Ion/Ioff and subthreshold factor of the Cross-Gate SOI device are almost the same with such of the Four Channels Multi-Gate SOI device.
    As far as the fabrication process is concerned, the new SOI device has simpler isolation processes than that of the conventional one. In addition, the nano-devices that Leff = 71nm was successfully fabricated. As concerning the electrical behavior, under the same condition of Leff = 71nm, Weff = 440nm, tsi = 120nm, the Cross-Gate SOI device has the lower subthreshold factor which is 93.153 and the higher Ion/Ioff which is 1.66×10E5 than those of the Four Channels Multi-Gate SOI device, in addition, the Cross-Gate SOI device has no kink effect. So, it can be concluded that such the Cross-Gate SOI device presented is much more applicable to the development of low power and high speed ULSI in the nearest future.
    Advisory Committee
  • Chia-Hsiung Kao - chair
  • Ting-Chang Chang - co-chair
  • Yau-Tsong Tsai - co-chair
  • Jyi-Tsong Lin - advisor
  • Files
  • etd-0112104-170701.pdf
  • indicate access worldwide
    Date of Submission 2004-01-12

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