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URN etd-0109114-110239
Author Ting-Chi Tung
Author's Email Address No Public.
Statistics This thesis had been viewed 5571 times. Download 422 times.
Department Computer Science and Engineering
Year 2013
Semester 1
Degree Ph.D.
Type of Document
Language English
Title Design and Implementation of Vector Graphics Accelerator Equipped with a Tessellation Processor
Date of Defense 2014-01-22
Page Count 153
Keyword
  • Tessellation
  • Rasterization
  • Adaptive Forward Difference
  • Scan-line Buffer
  • Vector Graphics
  • Abstract This dissertation presents an efficient and fast VLSI architecture of a vector graphics hardware accelerator. To render a vector graphics object, the contours of paths that constitute the object have to be plotted first. The outline of a path is described by a series of parametric segments, where the most frequently used type of segments are cubic Bézier curves (CBC). This dissertation presents an efficient intersection locator design used to generate the intersection information of cubic Bézier curves and scan-lines required for the two-dimensional (2D) graphics rasterization process. The conventional method of calculating the intersection point first approximates the curve with enough number of line segments and then solves two simultaneous equations of each line segment and scan-line. By extending the adaptive-forward-difference (AFD) algorithm to choose the proper successive sampling points of the curve, the proposed design can not only locate the intersection points precisely, but more importantly, it can avoid the use of complex functional units like multipliers and dividers which are typically used in solving simultaneous equations. The intersection information generated by our locator can lead to over 99.6 % accuracy.
    To tessellate the stroke contours of paths, this dissertation decomposes the stroke contours into a series of concatenated circular arcs and line segments. By transforming circular arcs and lines into the approximate cubic Bézier curves, all types of stroke contours can be plotted by homogeneous CBC processing modules. All the modules can be folded to a design that contains only one CBC tessellation core which can deal with all curve tessellation tasks including circular arcs and straight lines of stroke contours. To further reduce the control complexity required for utilizing the CBC core, a tessellation processor is proposed, which can be programmed to realize all the stroke functions. The burden of complex control circuit design can then been shifted to the coding of the control software. In addition to a main CBC core, the tessellation processor also contains several Look-up Tables (LUTs) to realize some complex arithmetic functions such as reciprocal, division, sine and cosine which are utilized while deriving the shell of the path.
    After the outlines of the vector graphics object have been tessellated, the filling regions of the object have to be found next in order to fill color. To decide the filling regions of the graphics object, a large on-chip scan-line buffer (SB) is very often used and frequently accessed to derive the pixel’s winding count. This dissertation proposes a special 2-bit coding scheme for each buffer entry along with the active-edge-table rescan method to record the intersection information of scan-lines and the object paths. In addition, for AA rendering applications, a coverage buffer is also proposed to avoid the duplication of SBs. Compared with the conventional approach, the required buffer size can be reduced by up to 89%. Besides buffer reduction, this dissertation also proposes a hierarchical SB architecture in which the upper-level buffer indicates which scan-line sections have intersected with objects in order to skip the access to successive buffer entries. The same technique, along with the differential coverage transformation, can also be applied to the coverage buffer. Our experimental results show that more than 87% of memory accesses can be reduced, which results in saving 66.4% of clock cycles in practical hardware implementation.
    The proposed vector graphics accelerator has been implemented based on SAED 90nm library, and can run up to 150 MHz. The total gate count of the rendering accelerator is about 225.06k, where the tessellation processor and rasterization accelerator consume about 199.32k and 16.76k gates respectively. The accelerator can render Tiger object over 45 frame per second (FPS) under the resolution of 240x320 pixels. The proposed accelerator can improve the overall rendering speed and is suitable for dedicated embedded applications.
    Advisory Committee
  • Pei-Yin Chen - chair
  • Shen-Fu Hsiao - co-chair
  • Yeong-Kang Lai - co-chair
  • Shiann-Rong Kuang - co-chair
  • Chung-Ho Chen - co-chair
  • Yun-Nan Chang - advisor
  • Files
  • etd-0109114-110239.pdf
  • Indicate in-campus at 2 year and off-campus access at 3 year.
    Date of Submission 2014-02-09

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