| URN |
etd-0013117-100446 |
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| Author |
Po-chao Huang |
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| Author's Email Address |
No Public. |
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| Statistics |
This thesis had been viewed 5537 times. Download 0 times. |
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| Department |
Computer Science and Engineering |
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| Year |
2016 |
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| Semester |
1 |
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| Degree |
Master |
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| Type of Document |
|
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| Language |
zh-TW.Big5 Chinese |
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| Title |
A High speed 12-bit Digital-to-Analog Converter with the extended encoding scheme |
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| Date of Defense |
2016-08-25 |
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| Page Count |
40 |
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| Keyword |
DAC
high speed
high precision
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| Abstract |
In the mobile communication applications, the Digital-to-analog converter (DAC) needs the higher accuracy and speed. However, the operation time is limited by the battery capacity of the mobile devices. Increasing speed and accuracy are the trend of the current DAC’s circuit design. In the conventional current source architecture of the high-speed applications, the limited dynamic linearity is affected by the excessive number of switches. Therefore, this thesis proposes a new coding method to design a current-steering architecture that the digital-to-analog converter can achieve a high-speed operation for different applications. The proposed DAC architecture is composed of an eight-bit thermometer code and a four-bit expanded encoder digital-to-analog converter. It mainly can reduce the number of times of a single switch. Hence, the circuit can achieve a better linearity to improve the dynamic performance.
Finally, the design was designed in TSMC 90nm CMOS process. The sample rate and resolution of the DAC are 1GS/s and 12-bit, respectively. The power consumption is 27.5mW. |
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| Advisory Committee |
Shiann-Rong Kuang - chair
Xin-Yu Shih - co-chair
Ko-Chi Kuo - advisor
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| Files |
Indicate in-campus at 5 year and off-campus access at 5 year. |
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| Date of Submission |
2017-01-24 |
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