現今網路的蓬勃發展以及無線網路的普及，除了傳輸的速度上升外，傳輸正確率也顯得更為重要，為避免在資料傳輸過程中因雜訊造成的資料錯誤，使資料可以正確傳輸。錯誤更正碼（ECC，error correction code）的概念在1940年代被Richard Hamming提出，並在1950提出了第一個錯誤更正碼漢明碼(Hamming code)，而在之後至今陸續有各種錯誤更正碼被提出，低密度奇偶檢查碼(Low-density parity-check code，LDPC code)、渦輪碼(Turbo code)以及本文的重點極化碼(Polar code)。極化碼為首個被證明能達到香農極限(Shannon's limit)的錯誤更正碼，代表著強大的錯誤更正能力，因此自其在2009年Erdal Arıkan首度提出後便成為通訊領域的新星，發展極其迅速，如今已應用在5G網路控制通道的更正錯誤上。
因極化碼隨著碼長的增長除錯性能會隨之上升，但編碼及解碼複雜度也會上漲，本論文針對極化碼連續消除解碼器（Successive cancellation decoder ，SC decoder）做了多模式(Multi-mode)設計，使其能在多個碼長間選擇，搭配折疊(Fold)技術以及特殊的量化(Quantization)方式，重複利用運算元件，降低面積且提高硬體使用率，並使用特殊硬體設計降低運算所需週期。利用極化碼凍結通道的特性，使用特殊的控制方案，降低運算複雜度以及儲存凍結碼所需儲存空間大小，更一步地降低運算週期，再加上重複利用模組化的暫存器架構，使得暫存器數量減半並降低控制複雜度，搭配上特製的介面，使其不會隨著碼長增長而降低運算頻率。在使用TSMC 40nm CMOS製程實現硬體，運用上述技術以達到低面積成本、高運算速度、高吞吐量等連續消除解碼器架構，期許能給如今的5G網路甚至未來的6G網路些許貢獻，建構出高速率、低延遲及高可靠度的解碼器架構設計，成為未來豐富應用的基石。

With the booming development of the Internet and the popularity of wireless networks, not only the speed of transmission has increased, but also the accuracy of transmission has become more important to avoid data errors caused by noise during data transmission and to enable correct data transmission. The concept of error correction codes was introduced by Richard Hamming in the 1940s, and the first error correction codes, Hamming, was introduced in 1950, and various error correction codes have been introduced since then, including low-density parity-checking codes, turbo codes, and polar codes. Polar codes are the first error-correcting codes that have been proven to reach Shannon's limit and represent a powerful error-correction capability, and therefore have become a rising star in the communication field since they were first proposed by Erdal Arıkan in 2009.
This thesis presents a multi-mode design for successive cancellation decoder, which allows to choose between multiple code lengths, with folding techniques and special quantization methods, reusing computational components and reducing area, and using special hardware design to reduce the calculation cycle. The freeze channel feature is used to reduce the complexity of computing and the amount of storage space required to store the frozen data by using a special control scheme to further reduce the computing cycle time. Using TSMC 40nm CMOS process to implement the hardware, the above technologies to achieve low area cost, high speed, high throughput. This successive cancellation decoder architecture is expected to make some contribution to 5G and even future 6G networks, constructing a high-speed, low-latency, and high-reliability design, which will be the cornerstone of rich applications in the future.

論文審定書 i
摘要 ii
Abstract iii
目錄 iv
圖次 vi
表次 viii
第一章 緒論 1
1.1 背景與動機 1
1.2 論文架構 4
第二章 極化碼介紹 5
2.1 極化碼原理 5
2.1.1 通道組合 5
2.1.1 通道分解 7
2.1.2 通道極化 8
2.2 連續消除解碼器 10
2.2.1 似然比解碼 10
2.2.2 對數似然比解碼 11
第三章 可變碼長架構超大型積體電路實現 13
3.1 系統簡介 13
3.2 技術一：新穎的折疊計算架構 15
3.2.1 摺疊 15
3.2.2 常規運算單元與量化分析 16
3.2.3 加速運算階層 22
3.3 技術二：高效凍結碼控制方案 25
3.3.1 跳躍式控制 25
3.3.2 部分和電路 27
3.3.3 結果分析 31
3.4 技術三：可完全重複運用儲存裝置 32
3.4.1 低延遲資料存取介面 33
3.4.2 低功耗設計 36
第四章 晶片實現 38
4.1 合成結果分析 39
4.2 可測試性設計 40
4.3 布局結果 42
4.4 效能比較 43
第五章 結論 44
參考文獻 45

[1] "智在未來" https://zhuanlan.zhihu.com/p/101979305
[2] "Error correction code." https://en.wikipedia.org/wiki/Error_correction_code
[3] R. Gallager, "Low-density parity-check codes," IRE Transactions on Information Theory, vol. 8, no. 1, pp. 21-28, 1962.
[4] C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1," in Proceedings of ICC '93 - IEEE International Conference on Communications, 23-26 May 1993 1993, vol. 2, pp. 1064-1070 vol.2.
[5] E. Arikan, "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, 2009.
[6] I. Tal and A. Vardy, "List Decoding of Polar Codes," IEEE Transactions on Information Theory, vol. 61, no. 5, pp. 2213-2226, 2015.
[7] K. Niu and K. Chen, "CRC-Aided Decoding of Polar Codes," IEEE Communications Letters, vol. 16, no. 10, pp. 1668-1671, 2012.
[8] B. Yuan and K. K. Parhi, "Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 4, pp. 1241-1254, 2014.
[9] C. Zhang, B. Yuan, and K. K. Parhi, "Reduced-latency SC polar decoder architectures," in 2012 IEEE International Conference on Communications (ICC), 10-15 June 2012 2012, pp. 3471-3475.
[10] C. Zhang and K. K. Parhi, "Low-Latency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder," IEEE Transactions on Signal Processing, vol. 61, no. 10, pp. 2429-2441, 2013.
[11] Y. Huang, Z. Zhang, X. You, and C. Zhang, "Efficient Folded SC Polar Line Decoder," in 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP), 19-21 Nov. 2018 2018, pp. 1-5.
[12] X. Bian, J. Dai, K. Niu, and Z. He, "A Low-Latency SC Polar Decoder Based on The Sequential Logic Optimization," in 2018 15th International Symposium on Wireless Communication Systems (ISWCS), 28-31 Aug. 2018 2018, pp. 1-5.
[13] G. Berhault, C. Leroux, C. Jego, and D. Dallet, "Partial sums computation in polar codes decoding," in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 24-27 May 2015 2015, pp. 826-829.
[14] C. Yun-Nan, "Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator," in 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 26-29 June 2016 2016, pp. 1-4.
[15] X. Liu et al., "A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET," in 2018 15th International Symposium on Wireless Communication Systems (ISWCS), 28-31 Aug. 2018 2018, pp. 1-5.
[16] O. Alsherbini, M. Wael, E. Fahmy, A. Helmy, Y. Ismail, and K. Salah, "ASIC Implementation of Energy-Optimized Successive Cancellation Polar Decoders for Internet of Things," in 2018 30th International Conference on Microelectronics (ICM), 16-19 Dec. 2018 2018, pp. 260-263.
[17] O. Dizdar and E. Arıkan, "A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 3, pp. 436-447, 2016.
 
[18] A. Mishra et al., "A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS," in 2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 12-14 Nov. 2012 2012, pp. 205-208.