半導體的製程中，為了使晶片的厚度與尺寸符合生產線之需求而須調整晶片的厚度，其中晶背研磨製程為晶圓減薄最常見的製程方式之一。但當晶圓厚度減至極薄時，因結構強度之下降，晶圓的翹曲情形將會更加顯著。晶背研磨製程中，需設定三個製程參數：砂輪轉速、晶圓轉速，以及進給率，因此需透過分析製程造成晶圓翹曲的原因，以找出製程參數和翹曲之間的影響。
本研究建立之晶背研磨翹曲預測模擬模型主要分為動態的晶圓殘餘應力預測模型，及穩態的晶圓翹曲預測模型兩個部分，並藉由實驗設計法(Design of Experiment, DoE)，對純矽晶圓及扇出型封裝兩結構之晶圓預測晶圓表面應力及其翹曲量，並對粗研磨及細研磨兩階段製程之各程參數進行比較，探討對晶圓造成翹曲的影響趨勢。由於晶背研磨製程是由研磨砂輪與晶圓之間相互影響的製程，亦藉由研磨砂輪力量方程式與晶圓表面殘餘應力進行分析，探討其之間是否有直接關係。
根據實驗數據的對照，從而建立精準度極高之翹曲預測模擬模型，並使用此研究方法探討後續結果，得知晶圓表面之應力分布如同心圓狀由內而外增加，並得知在相同的製程條件下順切研磨優於逆切研磨。製程參數中，砂輪轉速與晶圓翹曲呈現負相關，而晶圓轉速及進給率與晶圓翹曲呈現正相關。藉由田口設計法之分析，得知影響純晶圓翹曲及扇出型封裝翹曲程度之重要因子為細研磨之進給率；。本研究最後提出矽晶圓及扇出型封裝晶圓之最佳化參數設計，以有效降低晶圓之翹曲數值。

In the semiconductor manufacturing process, the thickness and size of die is necessary to adjust the requirement of the production line, the backside grinding process is most commonly used for this purpose. However, when the thickness of the wafer is reduced to thinner and thinner, the warpage of the wafer will be more significant due to the decrease in structural strength. Thus, to find the main factor of wafer thickness in wheel rotation speed, wafer rotation speed, and feed rate is necessary. Consequently, the influence of process parameters on wafer warpage was analyzed in the present study.
For this purpose, the warpage prediction simulation model of backside grinding process was established, comprising of explicit dynamic model for wafer residual stress prediction, and steady-state model aimed at wafer warpage prediction. The Design of Experiment (DoE) method was employed to estimate the surface stress and warpage of both silicon wafers and Fan-Out wafer-level packaging wafers, the parameters in the two-stage process (rough grinding and fine grinding) to be compared, and their influence on the wafer warpage to be analyzed. Since the grinding wheel and the wafer interact during the backside grinding process, the force of the grinding wheel and the residual stress on the wafer surface were also analyzed to establish the potential direct relationship between these factors.
As the proposed warpage prediction simulation model provided a high accuracy to the experimental data, it was also applied to explore the experimental results. In line with the extant empirical evidence, our results indicated that the stress distribution on the wafer surface increases radially from its center to its perimeter and that, under identical process conditions, down-grinding (whereby the tool rotates against the direction of the feed) is superior to up-milling (in which direction is the same). Moreover, the wheel rotation speed is negatively correlated, whereas the wafer rotation speed and feed rate are positively correlated with wafer warpage. By applying the Taguchi design method, the feed rate emerged as the main factor affecting silicon wafer warpage in fine grinding, whereas the warpage of Fan-Out wafer-level packaging wafer is predominantly influenced by the feed rate. However, when the studied design parameters are optimized, wafer warpage can be significantly reduced.

論文審定書 i
誌謝 ii
摘要 iii
Abstract iv
目錄 vi
圖目錄 viii
表目錄 xii
中英文對照表 xiv
第一章緒論 1
1.1前言 1
1.2研究背景 6
1.3研究動機 21
1.4研究主旨 21
第二章文獻回顧 25
2.1前言 25
2.2理論相關文獻 26
2.3實驗相關文獻 30
2.4模擬相關文獻 37
2.5Fan-Out相關文獻 42
2-6結論 46
第三章研究方法 51
3.1前言 51
3.2研究流程 55
3.3矽晶圓(Silicon Wafer)材料晶背研磨之研究方法 62
3.4扇出型晶圓級封裝晶圓(Fan-Out Wafer)材料之研究方法 67
3.5晶背研磨製程研磨砂輪力量理論方程式探討 72
3.6小結 79
第四章矽晶圓之研究結果與討論 81
4.1前言 81
4.2矽晶圓動態模擬模型之模型趨勢確認 82
4.3研磨力量方程式與動態模擬模型趨勢確認 88
4.3矽晶圓動態模擬模型之模型趨勢確認 90
4.4矽晶圓研磨方向組合與應力數值之比較 94
4.5一次因子分析法 100
4.6小結 108
第五章矽晶圓趨勢分析與Fan Out結構之分析 110
5.1前言 110
5.2矽晶圓研磨之田口設計分析及最佳化設計 111
5.3Fan-Out結構之晶背研磨製程應用 117
5.4Fan-Out結構之晶背研磨製程分析及最佳化設計 123
5.5小結 136
第六章結論與未來展望 138
6.1結論 138
6.2未來展望 140
參考文獻 142

[1] 晶圓研磨機台，取自https://tw.ttnet.net/products/jiuwn3bzjiujlqwhkh4a.html(引用日期：2021/10/22)
[2] Gao, S., Dong, Z., Kang, R., Zhang, B., & Guo, D. (2015). Warping of silicon wafers subjected to back-grinding process. Precision Engineering, Volume 40, 87-93.
[3] Pei, Z. J., & Strasbaugh, A. (2002). Fine grinding of silicon wafers: designed experiments. International Journal of Machine Tools and Manufacture, Volume 42, Issue 3, 395-404.
[4] Tummala, R., Sundaram, V., Raj, P. M., & Smet, V. (2017). Future of embedding and Fan-Out technologies. In 2017 Pan Pacific Microelectronics Symposium (Pan Pacific).
[5] Sun, J., Qin, F., Chen, P., & An, T. (2016). A predictive model of grinding force in silicon wafer self-rotating grinding. International Journal of Machine Tools and Manufacture, Volume 109, 74-86.
[6] Sharp, K. W., Miller, M. H., & Scattergood, R. O. (2000). Analysis of the grain depth-of-cut in plunge grinding. Precision engineering, Volume 24, Issue 3, 220-230.
[7] Pietsch, G. J., & Kerstan, M. (2005). Understanding simultaneous double-disk grinding: operation principle and material removal kinematics in silicon wafer planarization. Precision Engineering, Volume 29, Issue 2, 189-196.
[8] Sun, J., Chen, P., Qin, F., An, T., Yu, H., & He, B. (2018). Modelling and experimental study of roughness in silicon wafer self-rotating grinding. Precision Engineering, Volume 51, 625-637.
[9] Agarwal, S., & Rao, P. V. (2013). Predictive modeling of force and power based on a new analytical undeformed chip thickness model in ceramic grinding. International Journal of Machine Tools and Manufacture, Volume 65, 68-78.
[10] Wang, D., Ge, P., Bi, W., & Jiang, J. (2014). Grain trajectory and grain workpiece contact analyses for modeling of grinding force and energy partition. The International Journal of Advanced Manufacturing Technology, Volume 70, Issue 9-12, 2111-2123.
[11] Young, H. T., Liao, H. T., & Huang, H. Y. (2007). Novel method to investigate the critical depth of cut of ground silicon wafer. Journal of materials processing technology, Volume 182, Issue 1-3, 157-162.
[12] Tso, P. L., & Teng, C. C. (2001). A study of the total thickness variation in the grinding of ultra-precision substrates. Journal of Materials Processing Technology, Volume 116, Issue 2-3, 182-188.
[13] Liu, J. H., Pei, Z. J., & Fisher, G. R. (2007). Grinding wheels for manufacturing of silicon wafers: a literature review. International Journal of Machine Tools and Manufacture, Volume 47, Issue 1, 1-13.
[14] Pei, Z. J., Fisher, G. R., & Liu, J. (2008). Grinding of silicon wafers: a review from historical perspectives. International Journal of Machine Tools and Manufacture, Volume 48, Issue 12-13, 1297-1307.
[15] Hecker, R. L., Liang, S. Y., Wu, X. J., Xia, P., & Jin, D. G. W. (2007). Grinding force and power modeling based on chip thickness analysis. The International Journal of Advanced Manufacturing Technology, Volume 33, Issue 5-6, 449-459.
[16] Durgumahanti, U. P., Singh, V., & Rao, P. V. (2010). A new model for grinding force prediction and analysis. International Journal of Machine Tools and Manufacture, Volume 50, Issue 3, 231-240.
[17] Gao, S., Kang, R., Dong, Z., & Zhang, B. (2013). Edge chipping of silicon wafers in diamond grinding. International Journal of Machine Tools and Manufacture, Volume 64, 31-37.
[18] Tang, J., Du, J., & Chen, Y. (2009). Modeling and experimental study of grinding forces in surface grinding. Journal of materials processing technology, Volume 209, Issue 6, 2847-2854.
[19] Stoney, G. G. (1909). The tension of metallic films deposited by electrolysis. Proceedings of the Royal Society of London. Series A, Containing Papers of a Mathematical and Physical Character, Volume 82, Issue 553, 172-175.
[20] Chen, J., & De Wolf, I. (2003). Study of damage and stress induced by backgrinding in Si wafers. Semiconductor science and technology, Volume 18, Issue 4, 261.
[21] Zhou, L., Hosseini, B. S., Tsuruga, T., Shimizu, J., Eda, H., Kamiya, S., ... & Tashiro, Y. (2007). Fabrication and evaluation for extremely thin Si wafer. International Journal of Abrasive Technology, Volume 1, Issue 1, 94-105.
[22] Sun, J., Qin, F., Chen, P., & An, T. (2017). Residual stress distribution in wafers ground by different grinding parameters. In 2017 18th International Conference on Electronic Packaging Technology, 16 Aug – 19 Aug. China: Sun Island Garden Hotel.
[23] Pei, Z. J., & Strasbaugh, A. (2001). Fine grinding of silicon wafers. International Journal of Machine Tools and Manufacture, Volume 41, Issue 5, 659-672.
[24] Tian, Y. B., Kang, R. K., Guo, D. M., Jin, Z. J., & Su, J. X. (2004). Investigation on material removal rate in rotation grinding for large-scale silicon wafer. In Materials Science Forum, Volume 471, 362-368.
[25] Dalladay, A. J. (1922). Some measurements of the stresses produced at the surfaces of glass by grinding with loose abrasives. Transactions of the Optical Society, Volume 23, Issue 3, 170-174.
[26] Alvanos, T., Garant, J., Iijima, Y., Indyk, R., Rosenthal, C., Sato, O., ... & Wei, F. (2014). A novel methodology for wafer-specific feed-forward management of backside silicon removal by wafer grinding for optimized through silicon via reveal. In 2014 IEEE 64th Electronic Components and Technology Conference, 27 May – 30 May. USA: Walt Disney World Swan & Dolphin Resort.
[27] Yan, J., Asami, T., Harada, H., & Kuriyagawa, T. (2012). Crystallographic effect on subsurface damage formation in silicon microcutting. CIRP annals, Volume 61, Issue 1, 131-134.
[28] Draney, N. R., Liu, J. J., & Jiang, T. (2004). Experimental investigation of bare silicon wafer warp. In 2004 IEEE Workshop on Microelectronics and Electron Devices, 24 Oct – 27 Oct. USA: Portola Hotel & Spa at Monterey Bay.
[29] Zhou, L., Shimizu, J., & Eda, H. (2005). A novel fixed abrasive process: chemo-mechanical grinding technology. International journal of manufacturing technology and management, Volume 7, Issue 5-6, 441-454.
[30] Pandey, A., Dutta, S., Prakash, R., Dalal, S., Raman, R., Kapoor, A. K., & Kaur, D. (2016). Growth and evolution of residual stress of AlN films on silicon (100) wafer. Materials Science in Semiconductor Processing, Volume 52, 16-23.
[31] Huang, H., Wang, B. L., Wang, Y., Zou, J., & Zhou, L. (2008). Characteristics of silicon substrates fabricated using nanogrinding and chemo-mechanical-grinding. Materials Science and Engineering: A, Volume 479, Issue 1-2, 373-379.
[32] . Suratwala, T., Wong, L., Miller, P., Feit, M. D., Menapace, J., Steele, R., ... & Walmer, D. (2006). Sub-surface mechanical damage distributions during grinding of fused silica. Journal of non-crystalline solids, Volume 352, Issue 52-54, 5601-5617.
[33] Wang, Y., Zou, J., Huang, H., Zhou, L., Wang, B. L., & Wu, Y. Q. (2007). Formation mechanism of nanocrystalline high-pressure phases in silicon during nanogrinding. Nanotechnology, Volume 18, Issue 46, 465705.
[34] Zhou, L., Tian, Y. B., Huang, H., Sato, H., & Shimizu, J. (2012). A study on the diamond grinding of ultra-thin silicon wafers. Proceedings of the Institution of Mechanical Engineers, Part B: Journal of Engineering Manufacture, Volume 226, Issue 1, 66-75.
[35] Zhou, L., Eda, H., Shimizu, J., Kamiya, S., Iwase, H., Kimura, S., & Sato, H. (2006). Defect-free fabrication for single crystal silicon substrate by chemo-mechanical grinding. CIRP annals, Volume 55, Issue 1, 313-316.
[36] Zhang, L., & Zarudi, I. (2001). Towards a deeper understanding of plastic deformation in mono-crystalline silicon. International journal of mechanical sciences, Volume 43, Issue 9, 1985-1996.
[37] Yang, K. H. (1984). An etch for delineation of defects in silicon. Journal of the Electrochemical Society, Volume 131, Issue 5, 1140.
[38] Paehler, D., Schneider, D., & Herben, M. (2007). Nondestructive characterization of sub-surface damage in rotational ground silicon wafers by laser acoustics. Microelectronic Engineering, Volume 84, Issue 2, 340-354.
[39] Haapalinna, A., Nevas, S., & Pähler, D. (2004). Rotational grinding of silicon wafers—sub-surface damage inspection. Materials Science and Engineering: B, Volume 107, Issue 3, 321-331.
[40] Pogue, V., Melkote, S. N., & Danyluk, S. (2018). Residual stresses in multi-crystalline silicon photovoltaic wafers due to casting and wire sawing. Materials Science in Semiconductor Processing, Volume 75, 173-182.
[41] Jinglong, S., Fei, Q., Chao, R., Zhongkang, W., & Liang, T. (2014). Residual stress measurement of the ground wafer by Raman spectroscopy. In 2014 15th International Conference on Electronic Packaging Technology, 12 Aug – 15 Aug. China: University of Electronic Science and Technology of China.
[42] Sun, J., Qin, F., Ren, C., Wang, Z., & Liang, T. (2015). Residual stress measurement of the ground wafer by stepwise corrosion and Raman Spectroscopy. In 2015 16th International Conference on Electronic Packaging Technology, 11 Aug – 14 Aug. China: Central South University.
[43] Zhang, Y., Wang, D., Gao, W., & Kang, R. (2011). Residual stress analysis on silicon wafer surface layers induced by ultra-precision grinding. Rare Metals, Volume 30, Issue 3, 278-281.
[44] Teixeira, R. C., De Munck, K., De Moor, P., Baert, K., Swinnen, B., Van Hoof, C., & Knüttel, A. (2008). Stress analysis on ultra thin ground wafers. Journal Integrated Circuits and Systems, Volume 3, Issue 2, 83-89.
[45] Zhou, L. B., Yamaguchi, M., Shimizu, J., & Eda, H. (2007). Study on structure transformation of Si wafer in grinding process. In Key Engineering Materials, Volume 329, 373-378.
[46] Godin, J. R., Seong-hoon, P. W., Nieva, P. M., Phong, L. N., & Pope, T. Residual Stress Dependency on Wafer Location of Thin Film PECVD Silicon Nitride. Advanced Materials & Manufacturing, Volume 1, 108-111.
[47] Vrinceanu, I. D., & Danyluk, S. (2002). Measurement of residual stress in single crystal silicon wafers. In 2002 Proceedings. 8th International Advanced Packaging Materials Symposium.
[48] Kumar, A., Zhang, X., Zhang, Q. X., Jong, M. C., Huang, G., Vincent, L. W. S., ... & Meyer-Berg, G. (2011). Residual stress analysis in thin device wafer using piezoresistive stress sensor. IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume 1, Issue 6, 841-851.
[49] Murugesan, M., Fukushima, T., Bea, J. C., Lee, K. W., & Koyanagi, M. (2015). Yield enhancement and mitigating the Si-chipping and wafer cracking in ultra-thin 20µm-thick 8-and 12-inch LSI wafer. In 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference.
[50] Tian, Y. B., Zhou, L., Zhong, Z. W., Sato, H., & Shimizu, J. (2011). Finite element analysis of deflection and residual stress on machined ultra-thin silicon wafers. Semiconductor science and technology, Volume 26, Issue 10, 105002.
[51] 鄭本農. (2014). 晶圓製程之翹曲研究. 碩士論文, 台灣，新竹縣，中華大學.
[52] Abdelnaby, A. H., Potirniche, G. P., Barlow, F., Elshabini, A., Groothuis, S., & Parker, R. (2013). Numerical simulation of silicon wafer warpage due to thin film residual stresses. In 2013 IEEE Workshop on Microelectronics and Electron Devices (WMED), Apr 12. USA: Boise State University.
[53] Irving, S., & Liu, Y. (2003). Wafer deposition/metallization and back grind, process-induced warpage simulation. In Electronic Components and Technology Conference, 1 Jun – 4 Jun. USA: Sheraton San Diego Hotel & Marina.
[54] Mallik, A., & Stout, R. (2010). Simulation of process-stress induced warpage of silicon wafers using ANSYS® finite element analysis. In International Symposium on Microelectronics, Volume 1,364-371.
[55] Mallik, A., Stout, R., & Ackaert, J. (2014). Finite-element simulation of different kinds of wafer warpages: spherical, cylindrical, and saddle. IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume 4, Issue 2, 240-247.
[56] Schicker, J., Khan, W. A., Arnold, T., & Hirschl, C. (2016). Simulating the warping of thin coated Si wafers using Ansys layered shell elements. Composite Structures, Volume 140, 668-674.
[57] Ostrowicki, G. T., Gurrum, S. P., & Nangia, A. (2018). Correlated model for wafer warpage prediction of arbitrarily patterned films. In 2018 IEEE 68th Electronic Components and Technology Conference, 29 May – 1 Jun. USA: The Sheraton Hotel & Marina.
[58] Chen, Z., Zhang, X., Lim, S. P. S., Lim, S. S. B., Lau, B. L., Han, Y., ... & Andriani, Y. (2019). Wafer Level Warpage Modelling and Validation for FOWLP Considering Effects of Viscoelastic Material Properties under Process Loadings. In 2019 IEEE 69th Electronic Components and Technology Conference, 28 May – 31 May. USA: The Cosmopolitan Hotel.
[59] Kim, Y., Kang, S. K., Kim, S. D., & Kim, S. E. (2012). Wafer warpage analysis of stacked wafers for 3D integration. Microelectronic engineering, Volume 89, 46-49.
[60] Zhou, P., Xu, S., Wang, Z., Yan, Y., Kang, R., & Guo, D. (2016). A load identification method for the grinding damage induced stress (GDIS) distribution in silicon wafers. International Journal of Machine Tools and Manufacture, Volume 107, 1-7.
[61] Zhou, P., Yan, Y., Huang, N., Wang, Z., Kang, R., & Guo, D. (2017). Residual stress distribution in silicon wafers machined by rotational grinding. Journal of Manufacturing Science and Engineering, Volume 139, Issue 8.
[62] Zhu, C., Lee, H., Ye, J., Xu, G., & Luo, L. (2014). A new designed trench structure to reduce the wafer warpage in wafer level packaging process. In 2014 15th International Conference on Electronic Packaging Technology, 12 Aug – 15 Aug. China: University of Electronic Science and Technology of China.
[63] Huang, C. Y., Ng, D., Lee, H. H., Lin, V., Lin, C. F., & Chung, C. K. (2019). Process Induced Wafer Warpage Optimization for Multi-chip Integration on Wafer Level Molded Wafer. In 2019 IEEE 69th Electronic Components and Technology Conference, 28 May – 31 May. USA: The Cosmopolitan Hotel.
[64] Doman, D. A., Warkentin, A., & Bauer, R. (2009). Finite element modeling approaches in grinding. International journal of machine tools and manufacture, Volume 49, Issue 2, 109-116.
[65] Zhao, A. H., Xin, X. J., & Pei, Z. J. (2004). Implicit and explicit finite element simulation of soft-pad grinding of silicon wafers. In International LS-DYNA Users Conference, 2 May – 4 May. USA: The Hyatt Regency Dearborn Hotel & Conference Center.
[66] Xu, G., Zhu, C., Ye, J., Li, H., Gai, W., & Luo, L. (2014). Warpage and stress optimization of wafer-level package of MEMS with glass frit bonding. In 2014 15th International Conference on Electronic Packaging Technology, 12 Aug – 15 Aug. China: University of Electronic Science and Technology of China.
[67] Kwon, K., Lee, Y., Kim, J., Chung, J. Y., Jung, K., Park, Y. Y., ... & Kim, S. K. (2017). Compression molding encapsulants for wafer-level embedded active devices: Wafer warpage control by epoxy molding compounds. In 2017 IEEE 67th Electronic Components and Technology Conference, 30 May – 2 Jun. USA: Walt Disney World Swam & Dolphin Resort Lake Buena Vista.
[68] Tseng, C. F., Liu, C. S., Wu, C. H., & Yu, D. (2016). InFO (wafer level integrated Fan-Out) technology. In 2016 IEEE 66th Electronic Components and Technology Conference, 31 May – 3 Jun. USA: Spectacular Cosmopolitan Hotel.
[69] Braun, T., Becker, K. F., Wöhrmann, M., Töpper, M., Böttcher, L., Aschenbrenner, R., & Lang, K. D. (2017). Trends in Fan-Out wafer and panel level packaging. In 2017 International Conference on Electronic Packaging Technology, 16 Aug – 19 Aug. China: Sun Island Garden Hotel.
[70] Li, H. Y., Chen, A., Peng, S., Pan, G., & Chen, S. (2017). Warpage tuning study for multi-chip last fan Out wafer level package. In 2017 IEEE 67th Electronic Components and Technology Conference, 30 May – 2 Jun. USA: Walt Disney World Swam & Dolphin Resort Lake Buena Vista.
[71] Fan, X. J., Varia, B., & Han, Q. (2010). Design and optimization of thermo-mechanical reliability in wafer level packaging. Microelectronics Reliability, Volume 50, Issue 4, 536-546.
[72] Lin, T., Hou, F., Liu, H., Pan, D., Chen, F., Li, J., ... & Cao, L. (2016). Warpage simulation and experiment for panel level Fan-Out package. In 2016 IEEE CPMT Symposium Japan, 7 Nov – 9 Nov. Japan: Kyoto Grand Hotel.
[73] Lin, P. B., Ko, C. T., Ho, W. T., Kuo, C. H., Chen, K. W., Chen, Y. H., & Tseng, T. J. (2017). A comprehensive study on stress and warpage by design, simulation and fabrication of RDL-first panel level Fan-Out technology for advanced package. In 2017 IEEE 67th Electronic Components and Technology Conference, 30 May – 2 Jun. USA: Walt Disney World Swam & Dolphin Resort Lake Buena Vista.
[74] Su, M., Cao, L., Lin, T., Chen, F., Li, J., Chen, C., & Tian, G. (2018). Warpage simulation and experimental verification for 320 mm× 320 mm panel level Fan-Out packaging based on die-first process. Microelectronics Reliability, Volume 83, 29-38.
[75] Gadhiya, G., Brämer, B., Rzepka, S., & Otto, T. (2019). Assessment of FOWLP process dependent wafer warpage using parametric FE study. In 2019 22nd European Microelectronics and Packaging Conference & Exhibition, 16 Sep – 19 Sep. Italy: Hotel Galilei.
[76] Takekoshi, M., Nishido, K., Okada, Y., Suzuki, N., & Nonaka, T. (2017). Warpage suppression during FO-WLP fabrication process. In 2017 IEEE 67th Electronic Components and Technology Conference, 30 May – 2 Jun. USA: Walt Disney World Swam & Dolphin Resort Lake Buena Vista.
[77] Zhu, C., Guo, P., & Dai, Z. (2017). Investigation on wafer warpage evolution and wafer asymmetric deformation in Fan-Out wafer level packaging processes. In 2017 18th International Conference on Electronic Packaging Technology, 16 Aug – 19 Aug. China: Sun Island Garden Hotel.
[78] Liu, Y. C., Cheng, H. C., & Wu, Z. D. (2018). Molding Compound Effects on Warpage of Fan-Out Wafer Level Packaging. In 2018 20th International Conference on Electronic Materials and Packaging, 17 Dec – 20 Dec. China: Hong Kong University of Science Technology.
[79] Ho, J., Chen, R., Chen, K. Y., Shin, S., & Shih, M. K. (2018). Mechanical and Warpage Characterization of Glass Carrier in Fan-Out Technology Development. In 2018 19th International Conference on Electronic Packaging Technology, 08 Aug – 11 Aug. China: Crowne Plaza Shanghai Harbour City.
[80] Che, F. X., Ho, D., Ding, M. Z., & Zhang, X. (2015). Modeling and design solutions to overcome warpage challenge for Fan-Out wafer level packaging (FO-WLP) technology. In 2015 IEEE 17th Electronics Packaging and Technology Conference, 2 Dec – 4 Dec. Singapore: Marina Mandarin Hotel.
[81] Che, F. X., Yamamoto, K., Rao, V. S., & Sekhar, V. N. (2019). Panel warpage of Fan-Out panel-level packaging using RDL-first technology. IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume 10, Issue 2, 304-313.
[82] Nishimura, Y., Kisanuki, A., Hikaru, O., Masaki, I., & Kanagawa, N. (2019). ltra-Low Warpage and Excellent Filling Ability Liquid MUF for Advanced Fan-Out Wafer Level Package. n 2019 International Wafer Level Packaging Conference (IWLPC), 22 Oct – 24 Oct. USA: DoubleTree by Hilton Hotel San Jose.
[83] Frewein, M., Krivec, T., Tao, Q., Zuendel, J., Rosc, J., Gschwandl, M., & Fuchs, P. F. (2019). Package Level Warpage Simulation of a Fan Out System in Board Module. In 2019 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, 24 Mar – 27 Mar. Germany: Courtyard by Marriott Hannover Maschsee.
[84] Lau, J. H., Li, M., Tian, D., Fan, N., Kuah, E., Kai, W., ... & Yong, Q. (2017). Warpage and thermal characterization of Fan-Out wafer-level packaging. IEEE transactions on components, packaging and manufacturing technology, Volume 7, Issue 10, 1729-1738.
[85] Lau, J. H., Li, M., Yang, L., Li, M., Xu, I., Chen, T., ... & Xi, C. (2018). Warpage measurements and characterizations of Fan-Out wafer-level packaging with large chips and multiple redistributed layers. IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume 8, Issue 10, 1729-1737.
[86] Edwards, M. J., Bowen, C. R., Allsopp, D. W., & Dent, A. C. (2010). Modelling wafer bow in silicon–polycrystalline CVD diamond substrates for GaN-based devices. Journal of Physics D: Applied Physics, Volume 43, Issue 38, 385502.
[87] Hou, F., Lin, T., Cao, L., Liu, F., Li, J., Fan, X., & Zhang, G. Q. (2017). Experimental verification and optimization analysis of warpage for panel-level Fan-Out package. IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume 7, Issue 10, 1721-1728.
[88] Bertheau, J., Inoue, F., Phommahaxay, A., Iacovo, S., Rassoul, N., Sleeckx, E., ... & Nakamura, A. (2018). Extreme thinned-wafer bonding using low temperature curable polyimide for advanced wafer level integrations. In 2018 IEEE 68th Electronic Components and Technology Conference, 29 May – 1 Jun. USA: The Sheraton Hotel & Marina.
[89] 光學顯微鏡下之研磨顆粒，取自https://www.azom.com/article.aspx?ArticleID=5546 (引用日期：2021/10/22)