為了因應未來6G通訊技術需要能克服更險惡的環境，以及更龐大的資料傳輸和考量到晶片的成本，因此擁有邊解碼獨特性的極化碼將會是我們的研究對象，相較於主流的低密度奇同位元校驗(Low Density Parity Check, LDPC碼)，極化碼透過數學證明其通道容量可以達到香濃極限的技術，因此擁有更好的錯誤更正能力，也更能夠對抗險惡且千變換化的6G通訊環境之中。因此本架構期望能設計出高彈性的多模式晶片，其中包括更高的吞吐量、更好的解碼效能和低面積之設計，以實現一個能更符合商業化的晶片。
本論文將提出四項重要的技術，包括更少的排序級數和優良的管線化設計與平行化設計，以提升整體電路的吞吐量(Throughput)；高可靠度分段式循環冗餘校驗碼之封包架構設計，進而提升錯誤更正能力；改善硬體資料覆蓋的問題，進而提升演算法延遲過高的問題；低面積儲存單元設計，進而提高整體電路的硬體使用率。透過上述四項技術的提出，以及支援多模式設計，因此本研究主打高面積效率且具高彈性的晶片設計。
最終，透過TSMC 40nm CMOS至成實現本硬體架構，完成整體晶片設計的流程。

In order to address the requirements of future 6G communication technology, which will face more challenging environments and the need for larger data transmission while considering chip costs, our research focuses on polar codes with unique edge decoding capabilities. Compared to the mainstream Low Density Parity Check (LDPC) codes, polar codes have demonstrated through mathematical proofs their ability to achieve the Shannon capacity limit. This provides them with superior error correction capabilities, making them better suited to combat the complex and dynamic communication environments of 6G.
Thus, this framework aims to design highly flexible multi-mode chips, encompassing higher throughput, efficient decoding performance, and compact designs to achieve a more commercially viable chip. This paper introduces four crucial techniques:
(a) Reduced sorting stages and excellent pipelining and parallelism designs to enhance the overall circuit throughput.
(b) Packet architecture design for high-reliability segmented cyclic redundancy check codes to boost error correction capabilities.
(c) Improvement in hardware data coverage to mitigate algorithm latency issues.
(d) Low-area storage unit design to increase the hardware utilization of the overall circuit.
Through the implementation of these four techniques and support for multi-mode design, this study emphasizes high area efficiency and chip flexibility in its design. Finally, the hardware architecture is realized using TSMC's 40nm CMOS process, concluding the entire chip design process.

目錄
論文審定書........................................................................................................................i
誌謝...................................................................................................................................ii
摘要..................................................................................................................................iii
Abstract………………………………………………………………………………….iv
圖次.................................................................................................................................vii
表次...................................................................................................................................x
第一章 緒論 1
1.1 背景 1
1.2 動機與設計目標 3
第二章 極化碼介紹 6
2.1 極化碼理論 6
2.2 連續消除列表解碼演算法 9
2.3 連續消除解碼和連續消除反轉演算法之解碼流程 10
第三章 可支援雙演算法且多模式的高面積效率極化碼解碼器 12
3.1 系統介紹 12
3.1.1 系統主架構與模式選擇分析 12
3.1.2 演算法運算之硬體優化 16
3.1.3 控制單元(Control Unit) 17
3.2 技術一：低延遲之多位元樹葉節點解碼器 18
3.2.1 排序重要性 18
3.2.2 三級排序器與路徑當量平行化設計 19
3.2.3 時序排程與管線化設計 24
3.2.4 延遲分析 26
3.3 技術二：具高可靠度之非規律化循環冗餘校驗封包架構設計 29
3.3.1 循環冗餘校驗碼長度與錯誤偵測分析探討 29
3.3.2 非規律化分段式循環冗餘校驗封包架構設計與實現 32
3.3.3 效能分析 36
3.4 技術三：部分和暫存器資料覆蓋問題優化 38
3.4.1 樹葉節點可靠度判斷器(LNRJ)實現 39
3.4.2 反轉路徑判斷器(FPJ) 40
3.4.3 延遲分析 45
3.5 技術四：低面積儲存單元設計 49
3.5.1 高使用率儲存架構 49
3.5.2 非規律量化設計 52
3.5.3 非規律運算單元架構與多工器優化 54
3.5.4 面積分析 59
第四章 晶片實現 62
4.1 標準單元晶片設計流程 62
4.2 合成結果分析 63
4.3 可測試性晶片設計與分析 65
4.4 形式驗證(FORMAL VERIFICATION) 67
4.5 晶片佈局成果 68
4.6 效能比較 69
第五章 結語與未來展望 74
5.1 結語 74
5.2 未來展望 74
參考文獻 75 

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