隨著神經網路的蓬勃發展，複雜的模型架構逐漸問世。傳統硬體架構無法兼具高資料吞吐與高操作頻率，因此專門設計給神經網路的硬體架構已成為開啟AI世代的一把鑰匙。且為了操作過程的穩定與可靠性，環境變異的偵測成為重要的角色。本論文首先針對溫度偵測器提出新型的架構，提高可偵測的溫度範圍並達到高線性度、高解析度的表現。本論文另外配合TSMC JDP 產學合作案，提出針對卷積網路優化的高效能硬體加速器與光學卷積神經網路架構。
本論文第一個研究主題為高線性和高解析之大範圍溫度偵測器，係以正、負溫度係數電流產生器，搭配可調節差動對之延遲震盪單元組成的電流頻率轉換器，得到兩組因溫度呈現相反特性的頻率，經由頻率相除減少同相誤差和提高溫度間的差異。本設計可偵測之溫度範圍為-40 ◦C ~ 100 ◦C，並能偵測每0.5 ◦C 溫度變化，晶片量測的最大線性誤差為0.436 %。
本論文第二個研究主題包含兩大電路系統，分別為高效能神經網路硬體加速器與光學神經網路架構。第一系統係提出專門用於卷積運算的新型硬體架構，係以高度平行化的運算單元陣列、記憶體資料處理的Reshpae 模組、允許同步讀取與計算的設計，晶片量測可達54.61 GOPS 與96.35 mW 的高效能成果。第二系統提出新穎的光學卷積神經網路架構，係以光學晶片高速且低功耗的特點，處理大量繁瑣的卷積運算，配合電學電路進行特萃取，達成首例光電整合的神經架構。並在一萬筆MNIST 手寫辨識中，具有93.8% 的辨識率。

As neural networks flourish, many sophisticated models are emerging. Traditional hardware architectures struggle to achieve high throughput and low power at the same time. Consequently, hardware architectures meticulously designed for neural networks have become an indispensable key to resolve the mentioned issues. Ensuring stability and reliability during any operation, the on-chip sensors play a pivotal role. The first topic in this thesis presents a novel architecture for temperature sensing, enhancing the detectable temperature range while achieving high linearity and high resolution. Additionally, thanks to the support of TSMC JDP project, this thesis secondly presents an efficient hardware accelerator optimized for convolution neural networks (CNN) and an innovative photonic
neural network architecture.
The high-linearity and high-resolution wide range temperature detector employing PTAT and CTAT current generators is coupled to a current-to-frequency converter composed of differential delay cells. Two frequency sets with opposite temperature characteristics are attained. By the division of these frequencies, common-mode errors are reduced enhancing the differentiation in temperature variations. The proposed sensor can measure temperatures range from -40 ◦C ~ 100 ◦C with 0.5 ◦C resolution. Maximum linearity error of 0.436 % is found by on-silicon measurement.
The second topic includes two systems: a high-performance neural network hardware accelerator and a photonic neural network architecture. The first system presents a novel hardware architecture specifically designed for convolutional computations. Besides a highly parallelized PE array, the hardware accelerator is featured with a reshape module for memory data processing, which allows synchronous reading and computation. The on-silicon measurement shows the performance of 54.61 GOPS at 96.35 mW. The second system presents an innovative photonic neural network (PNN) structure. Take advantage of the high-speed and low-power consumption advantages of optical devices, extensive convolutional computations combined with feature extraction is realized. Based on 10,000 MNIST benchmark testing, the recognition rate of 93.8% is achieved.

論文審定書. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
論文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
1 背景說明與研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 前言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 相關文獻探討. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 溫度偵測器架構介紹. . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 類神經網路硬體加速器. . . . . . . . . . . . . . . . . . . . . . 6
1.2.3 光學神經網路介紹. . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.1 高線性與高解析之大範圍溫度偵測器. . . . . . . . . . . . . . 8
1.3.2 高效能神經網路硬體加速器、光學卷積神經網路架構. . . . 9
1.4 論文大綱. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 高線性與高解析之大範圍溫度偵測器. . . . . . . . . . . . . . . . . . . . . 12
2.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 系統架構與原理說明. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 系統之子電路設計與分析. . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 正溫度係數(PTAT) 頻率產生器. . . . . . . . . . . . . . . . . 13
2.3.2 負溫度係數頻率產生器. . . . . . . . . . . . . . . . . . . . . . 15
2.3.3 電流頻率轉換器. . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.4 測試電路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4 電路模擬結果與預計規格. . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 電路佈局前後模擬比較. . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.6 晶片佈局與晶片照相. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.7 晶片量測環境及結果. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.7.1 量測環境與設定. . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.7.2 量測結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.8 量測結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.8.1 量測結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.8.2 量測結果與佈局後模擬比較分析. . . . . . . . . . . . . . . . 39
2.9 電路規格以及與先前文獻比較. . . . . . . . . . . . . . . . . . . . . . 42
2.9.1 電路規格比較與分析. . . . . . . . . . . . . . . . . . . . . . . 42
2.9.2 與先前文獻比較. . . . . . . . . . . . . . . . . . . . . . . . . . 42
3 高效能神經網路硬體加速器與
光學卷積神經網路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.1 簡介與架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2 第一電路系統-類神經網路原理說明. . . . . . . . . . . . . . . . . . . 46
3.3 第一電路系統-硬體加速器電路原理與設計. . . . . . . . . . . . . . . 50
3.3.1 處理單元陣列(PE array) . . . . . . . . . . . . . . . . . . . . . 50
3.3.2 Reshape and Line Buffer . . . . . . . . . . . . . . . . . . . . . . 52
3.3.3 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3.4 靜態隨機存取記憶體(SRAM) . . . . . . . . . . . . . . . . . . 54
3.4 硬體加速器模擬與效能分析. . . . . . . . . . . . . . . . . . . . . . . 57
3.4.1 類神經網路加速器系統模擬. . . . . . . . . . . . . . . . . . . 57
3.4.2 Clock Tree 分析. . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.4.3 可測試性設計(Design for Testability, DFT) 模擬結果. . . . . . 62
3.5 DLA 晶片實現. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.6 DLA 晶片量測. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.6.1 DLA 量測環境. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.6.2 DLA 之狀態機跳轉量測結果. . . . . . . . . . . . . . . . . . . 64
3.7 DLA 電路規格與文獻比較. . . . . . . . . . . . . . . . . . . . . . . . 67
3.8 第二電路系統-光學卷積神經網路電路與架構. . . . . . . . . . . . . . 69
3.8.1 PNN 原理與光學晶片. . . . . . . . . . . . . . . . . . . . . . . 70
3.8.2 全連接層之Hidden Layer 層模擬. . . . . . . . . . . . . . . . 71
3.8.3 ZCU111 全連接層電路架構. . . . . . . . . . . . . . . . . . . . 72
3.8.4 DAC 與ADC 電路系統. . . . . . . . . . . . . . . . . . . . . . 73
3.9 PNN 模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.9.1 FPGA 模擬與分析. . . . . . . . . . . . . . . . . . . . . . . . . 74
3.9.2 PNN 實驗與結果. . . . . . . . . . . . . . . . . . . . . . . . . 75
3.10 兩大電路系統測試結果與討論. . . . . . . . . . . . . . . . . . . . . . 76
3.10.1 DLA 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . 76
3.10.2 PNN 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . 77
4 結論與未來研究方向. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.1 研究結果與結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.2 未來研究方向. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2.1 高線性與高解析之大範圍溫度偵測器. . . . . . . . . . . . . . 79
4.2.2 高效能神經網路硬體加速器與光學卷積神經網路. . . . . . . 80
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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