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博碩士論文 etd-0501122-114656 詳細資訊
Title page for etd-0501122-114656
論文名稱
Title
在VIVADO平台上QPSK數據機的設計與模擬
Design and Simulation of QPSK Modem on the VIVADO Platform
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
91
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2022-05-30
繳交日期
Date of Submission
2022-06-01
關鍵字
Keywords
不同相位訊號、發射機、接收機、取樣、Verilog
Signal of different phases, Transmitter, Receiver, Sampling, and Verilog
統計
Statistics
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The thesis/dissertation has been browsed 1075 times, has been downloaded 0 times.
中文摘要
在一個容易受到干擾的環境中,無線通訊的數據機(MODEM)為了降低位元錯誤率(Bit Error Rate, BER)只能使用簡單設計的調變技術,但是另一方面,為了提高資料的傳輸速率(Data Rate, DR),數據機必須使用較為複雜設計的調變技術,使用複雜設計的調變技術很容易因為訊號的相互干擾而造成位元錯誤率的增加。為了能降低BER但又不過度的犧牲DR,本論文使用不同相位的訊號來設計數據機以降低訊號傳輸時的複雜度,此數據機由兩個部分所組成,分別為發射機與接收機,發射機的設計原理是將使用者產生的資料,以幾個位元(Bits)為一組先與系統的時序(Clock)做同步後,再將每一個位元組轉換成不同相位的訊號傳送出去,接收機的設計原理是先將收到的訊號做取樣(Sampling)以辨別不同的相位後,再將不同相位的訊號轉換回使用者的原始資料。最後,我們在XILINX的VIVADO平台上使用Verilog硬體描述語言來模擬所設計的發射機與接收機,從模擬的結果中,我們驗證所設計的發射機能傳送不同相位的訊號並且能在接收機上正確還原使用者的原始資料。
Abstract
In an interference-prone environment, wireless communication modulator and demodulator (MODEM) can use only simple-designed modulation techniques to reduce bit error rates (BER), on the other hand, in order to increase data rates (DR), the design of a MODEM should employ more complex modulation techniques. However, using complex modulation techniques might increase BER due to the mutual interference of signals. In order to reduce BER without unduly sacrificing DR, this thesis designs a MODEM with signals of different phases to reduce the complexity of signal transmission. The MODEM in our design consists of two parts - transmitter and receiver. The design of a transmitter is to transmit user-generated data, after taking several bits as a group. Then, by synchronizing a group of bits with the system clock, the transmitter converts data into signals of different phases before transmitting out. The main contribution of a receiver is to do sampling on the received signals to distinguish different phases. At last, the receiver converts the received signals of different phases back to the original user data. We simulate the design of the transmitter and the receiver using the Verilog hardware description language on the VIVADO platform from XILINX. From the results of simulation, we validate that the transmitter is able to transmit signals of different phases and capable to restore the original user data on the receiver correctly.
目次 Table of Contents
論文審定書 i
致謝 ii
摘要 iii
Abstract iv
目錄 v
圖目錄 vii
表目錄 ix
第一章 導論 1
1.1 研究動機 1
1.2 研究方法 2
1.3 章節介紹 3
第二章 類比訊號的調變 4
2.1 資料與訊號 4
2.2 數位資料與類比訊號的傳輸 10
2.3 訊號調變技術 11
2.4 VIVADO平台 16
2.5 相關文獻 19
第三章 QPSK調變技術的設計 22
3.1 QPSK數據機 22
3.2 QPSK發射機 23
3.3 QPSK接收機 29
第四章 VIVADO的模擬與結果討論 38
4.1 QPSK數據機的硬體模組 38
4.2 VIVADO平台模擬 40
4.3 設定模擬的參數 56
4.4 模擬訊號與結果討論 58
第五章 結論與未來工作 65
5.1 結論 65
5.2 遭遇的困難 65
5.3 未來工作 66
Reference 67
Acronyms 73
Index 76

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